Real Time Generation of the Quinquenary Pulse Compression Sequence using FPGA

Quinquenary codes have been widely used in radar and communication areas, but the design of Quinquenary codes with good merit factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. All these optimization algorithms have serious drawbacks of non guaranteed convergence, slow convergence rate and require large number of evaluations of the objective function. To overcome these drawbacks, recently we proposed an efficient VLSI architecture for identification of the Quinquenary Pulse compression sequences. Integrating this architecture with the currently proposing architecture provides an efficient real time Hardware solution for identification and generation of the Quinquenary Pulse compression sequences. This paper describes the real time generation of the Quinquenary Pulse compression sequences using Field Programmable Gate Array (FPGA). In this paper an effort is made for the generation of the Pulse compression sequences using an efficient VLSI architecture. The Proposed VLSI architecture is implemented on the FPGA as it provides the flexibility of reconfigurability and reprogrammability. Key-Words: Pulse compression, Quinquenary sequence, VLSI architecture, FPGA, Merit Factor, Behavioral Simulation.